The present invention relates to electronic circuits; more particularly, to a semiconductor memory apparatus with repair circuits.
Generally, conventional semiconductor memory apparatuses include a plurality of cells for storing lots of data. After fabrication of a semiconductor memory apparatus, various tests are executed for checking whether all fabricated cells of the semiconductor device have errors. In case that some of the cells in the semiconductor memory apparatus have an error, i.e., some cells are defective, a favorable yield of a semiconductor fabrication process can not be achieved if the semiconductor memory apparatus is considered as a bad device due to only a few defective cells.
The semiconductor memory apparatuses have some redundant cells that can be substituted for the defective cells. Through a repair process, the defective cells are replaced by the redundant cells, respectively. If a defective cell is accessed, i.e., an address corresponding to the defective cell is inputted to a semiconductor memory apparatus, a redundant cell that has been substituted for the defective cell is accessed instead, by the change of an address transferring path. Generally, the change of the address transferring path is accomplished through blowing fuses.
Once an address is inputted to a semiconductor memory apparatus, the semiconductor memory apparatus checks whether the inputted address should be substituted with a repaired address or not. In case of a repaired address, the semiconductor memory apparatus accesses data of a redundant cell and alternatively, in case of a normal address (not repaired address), the semiconductor memory apparatus accesses data of a normal cell. Therefore, the semiconductor memory apparatus having redundant cells includes a detecting circuit for checking whether an inputted address is a repaired address or not. The detecting circuit generates a detecting signal having information about the checking result.
Each address that is inputted may have a different delay time since each address has a different signal transferring path. Therefore, it is difficult for the detecting circuit to generate the detecting signal at a predetermined regular timing regardless of each address inputted.